Intel has made significant strides in advanced chip packaging technology, introducing breakthrough innovations that could reshape how processors handle power delivery and memory integration. At the Electronic Components Technology Conference (ECTC), the semiconductor giant revealed several cutting-edge packaging solutions designed to meet the growing demands of artificial intelligence workloads and next-generation computing architectures.
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| A graphical representation of EMIB technology's scalability projected for 2023, 2026, and 2028, emphasizing its growing importance in meeting the demands of artificial intelligence workloads |
EMIB-T Technology Revolutionizes Chip Packaging
The centerpiece of Intel's announcements is EMIB-T, an enhanced version of the company's existing Embedded Multi-die Interconnect Bridge (EMIB) technology. This new approach incorporates through-silicon vias (TSVs) into the silicon bridge that connects different chiplets within a package. The innovation addresses a critical limitation of previous EMIB designs, which suffered from voltage droop issues due to their cantilevered power delivery architecture.
EMIB-T fundamentally changes the power delivery paradigm by routing electricity from the bottom of the chip package through TSV bridge dies. This creates a direct, low-resistance pathway that dramatically improves power efficiency and enables support for high-bandwidth memory technologies like HBM4 and HBM4e. The technology also boosts die-to-die communication bandwidth, supporting UCIe-A interconnect standards with data transfer rates of 32 Gb/s or higher.
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| A comparison of current architecture and EMIB-T technology, highlighting improvements in power delivery and noise reduction critical for enhanced chip packaging |
Scaling Capabilities and Interconnect Density
The new packaging technology enables substantially larger chip packages, reaching dimensions of 120x180mm while supporting more than 38 bridges and over 12 reticle-sized dies in a single package. Intel has achieved significant progress in interconnect density as well. While the first-generation EMIB featured a 55-micron bump pitch and the second generation scaled to 45 microns, EMIB-T maintains the 45-micron capability while promising support for pitches well below this threshold. The company plans to reach 35-micron pitches soon and has 25-micron pitches in active development.
Thermal Management Innovations
Recognizing the cooling challenges posed by increasingly powerful AI processors, Intel has developed a disaggregated heat spreader design that separates the heat spreader into distinct flat plate and stiffener components. This approach improves coupling with thermal interface materials and reduces solder voids by 25 percent. The company's illustrations showcase heat spreaders with integrated micro-channels for direct liquid cooling, capable of handling processors with thermal design power ratings up to 1,000W.
Enhanced Manufacturing Processes
Intel has also refined its thermal compression bonding techniques specifically for large package substrates. The new process minimizes thermal differences between package substrates and dies during bonding, resulting in improved yield rates and reliability metrics. This advancement enables the production of larger chip packages than previously possible in high-volume manufacturing while supporting finer pitches for EMIB connections.
Strategic Implications for Intel Foundry
These packaging innovations serve Intel's broader foundry ambitions, providing comprehensive chip production options for both internal use and external customers. The technology allows clients to integrate components from multiple vendors into single packages, reducing the risk associated with transitioning entirely to Intel's process nodes. Current Intel Foundry customers include major players like AWS and Cisco, as well as U.S. government projects RAMP-C and SHIP. Advanced packaging services represent the fastest revenue generation path for Intel Foundry, as they require shorter lead times compared to leading-edge process node chip production.